How to Ensure the Quality of Digital Video Signal

key word:

Digital video, signal quality

In the process of maintaining signal quality, digital TV equipment engineers often encounter instantaneous mutation of digital signal. The eye diagram and jitter display of waveform monitor introduced in this paper is a tool to measure the quality of digital transmission signal. If the error detection and processing e are correctly implemented in the system, it will help to monitor the key signal path and alarm the potential problems in the system.

The transition from analog system to digital system provides many advantages to help maintain the quality of video signal in equipment. After the video signal is converted to the digital domain, it will no longer be affected by a variety of analog phenomena that may affect the signal quality. By digitizing a high-quality video signal, many analog defects in the signal can be eliminated. However, in order to process signals in the digital domain, some common engineering practices need to be changed.

For example, the serial digital interface (SDI) is usually quite reliable, but at some points, the integrity of the transmitted signal cannot be guaranteed, and the data may have digital cliff. The clock of SDI is embedded in the data stream. If the receiving device cannot recover the clock, it cannot recover the video data and display image. Unfortunately, unlike analog systems (where signal deterioration occurs gradually), image degradation in digital systems occurs almost instantaneously. Therefore, the responsibility of digital TV Equipment Engineer is to maintain signal quality and prevent digital mutation.

In order to verify the installation quality, a specific pressure test signal can be applied to the system through an appropriate test mode generator. SDI check field is a special test signal, which includes two parts, as shown in Figure 1. Part of the SDI check field tests the operation of the equalizer by generating a 0000 0001 (or 1111 1111 11110) sequence. When the scrambler obtains the required starting conditions, this test is performed almost once for each field and will continue until terminated by the EAV packet. The sequence produces a higher DC component, which fully tests the simulation ability of the equipment and the transmission system of processing signals. Another part of the SDI check field signal is designed to check the performance of the PLL. It uses a special signal composed of 20 zeros and 20 ones, which provides the least number of zero crossings for clock extraction.

This kind of test is very helpful. It can verify the consistency of the digital system or test whether the system has stopped service. However, after the system is installed, how to monitor its status to ensure that there is no digital mutation in the signal or that there is no fault in a certain equipment?

EDH (Error DetecTIon and

The basis of handling is to insert cyclic redundancy code (CRC) calculation for each video field in the vertical auxiliary data area. The whole field and moving image have separate CRC, which are sent together with other serial data through the transmission system together with the status flag. The CRC will be recalculated in the deserializer. If the calculated CRC value is inconsistent with the transmission value, an error will be reported. Therefore, this method can be used to monitor SDI signals during service; Most video devices can now support embedding EDH in the vertical auxiliary data area. Various waveform monitors and SDI analyzers can provide status reports of EDH conditions and record errors, as shown in Figure 2. Typical error detection data is provided in the form of error seconds over a period of time and the time since the last second of the error. If the monitoring equipment reports frequent EDH errors, it indicates that the SDI signal is close to digital mutation. The signal path should be further checked to find and solve the problem.

In order to separate such problems in digital system, a waveform monitor capable of displaying SDI signal eye diagram is needed. In order to carry out accurate measurement, it is very important to use a cable with short length and high quality. The eye diagram is composed of overlapping parts in the sampling data stream until the amount of data change is sufficient to produce the three eye display shown in Fig. 3. On some instruments, it is also possible to associate the eye diagram display with the data word boundary (10 words for SD and 20 words for HD). This function is very useful for detecting jitter modes related to parallel serial conversion.

The serial receiver determines whether the signal is "high" or "low" in the center of each eye diagram, so as to detect the serial data. Because the noise and jitter in the signal are increasing in the transmission channel, they may close the eye diagram and reduce the availability of the received signal.

SMPTE standard specifies the requirements for signal transmission amplitude, jitter, overshoot and rise / fall time, as shown in Table 1.

The amplitude of the signal is important for two reasons. First, it is related to noise; Second, the receiver estimates the required high-frequency compensation (equalization) based on the remaining half clock frequency energy when the signal arrives. If the amplitude of the transmitter is incorrect, it may cause the receiver to adopt wrong equalization, resulting in signal distortion.

As defined in Table 1, the rise time and fall time are determined between 20% 80% amplitude points. Incorrect rise time may lead to signal distortion, such as oscillation and overshoot; If the rise time is too long, the time available for sampling in the eye diagram may be reduced. The overshoot on the rising and falling edges must not exceed 10% of the signal waveform. Overshoot may be caused by incorrect rise time, but it is more likely to be caused by discontinuous impedance or poor return loss in receiving and transmitting termination.

Jitter is shown as bold horizontal trace in eye diagram. The expansion degree of eye diagram will decrease with the increase of jitter until the receiver cannot decode the data. The jitter is measured by unit interval (UI). 1ui corresponds to the clock cycle: SD is 3.7ns and HD is 673.4ps. The effect of jitter on the system also depends on the frequency of jitter. SMPTE defines different frequency bandwidths for measuring jitter. Timing jitter is an overall measure of jitter in the transmission signal, and calibration jitter can separate jitter components that reduce the ability of the receiver to recover data.

The dithering animation shown in Fig. 4 shows the curve of peak to peak dithering related to video line and field rate corresponding to time. In this way, the jitter can be characterized according to the timing of the video signal. Many jitter related problems are caused by the transfer of synchronous phase lock (genlock) reference jitter to serial system. Such jitter is usually between 20Hz and hundreds of Hz. The phase detection process adopted by the synchronous phase-locked system may also increase noise, which will affect the jitter in the range of 10Hz 1kHz. Using appropriate bandwidth limiting filters, specific jitter components can be included or suppressed in jitter measurement.

The eye diagram and jitter display of waveform monitor are optional tools for measuring the performance of digital transmission signal. If EDH is correctly implemented in the system, it can help monitor key signal paths and alarm potential problems in the system. The key to maintaining the correct operation of the system is to use carefully designed equipment to ensure that its cable type, cable length and equipment termination meet the requirements.

How to Ensure the Quality of Digital Video Signal 1

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